Understanding how to burn eFuses on i.MX8 and i.MX8x families
On the i.MX8 and i.MX8x families the OTP (One Time Programmable) memory is part of the security subsystem and is controlled by the SCU (System Controller Uni...
Recent Posts
How to use UUU to flash the iMX boards
UUU is the next version of MFGTools, a tool used to load the software on the RAM or flash it to a list of boot media supported by several i.MX boards. UUU is...
System Controller Unit (SCU) Introduction for i.MX 8QXP MEK
The newly released i.MX 8QXP introduces a new concept for manipulating resource allocation, power, clocking and IO configuration and muxing. Due to the archi...
Enabling Cortex-M4 on i.MX 8QXP MEK
The i.MX 8QuadXPlus Multisensory Enablement Kit (MEK) is a NXP development platform based on Cortex A-35 + Cortex-M4 cores. Built with high-level integration...
i.MX 8QXP MEK launch and preview
The i.MX 8QXP MEK is the latest release from NXP’s i.MX 8 family. This is the most powerful i.MX to date and promises capabilities directed to the industrial...
How to dump the SDCard content to an image file
This post shows a way to dump the content of a booting SDCard to an image file with purpose of duplicating the SDCard or sharing its image.
How to run and debug the Cortex-M4 on i.MX 7ULP using IAR Embedded Workbench
This post covers the required steps to setup the MCUXpresso BSP and IAR toolchain to run and debug the Cortex-M4 on the i.MX 7ULP SoC.
How to use dual display on i.MX8 including 4k decoding
In this first post about i.MX 8M SoCs, you can check how easy is to use one or two HDMI displays and decoding 4k video file at 60fps in the i.MX 8MQ EVK.
i.MX 7ULP possible fix for U-Boot hang on “Starting kernel”
Sometimes when working with i.MX 7ULP the Cortex-A7 loading process can get stuck in the “Starting kernel” message. This can happen for many reasons, but a v...
i.MX 7ULP Heterogeneous Architecture and Different Boot Modes
The i.MX 7ULP is an heterogeneous SoC that presents a power domain architecture different than the other i.MX SoCs. In this architecture, both cores have con...